VLSI Formula Sheet

NMOS: Vout = Min[Vin, VG − VTn]
PMOS: Vout = Max[VG + |VTp|, Vin]

nFET → strong-0, weak-1 (VDD−VTn). pFET → strong-1, weak-0 (|VTp|).

2 · CMOS Logic Design

#transistors = #literals(f′)
PDN(NMOS): AND→series, OR→parallel
PUN(PMOS) = dual of PDN

2:1 MUX (TG): F = P0·s′ + P1·s

Transmission gate = nFET‖pFET, no threshold loss.

3 · Interconnect RC / Layout

R = ρl/A
Rs = ρ/t   [Ω/sq]
R_line = Rs·n , n = l/w

Corner square = 0.635 × normal square.

C_line = εox·w·l / Tox
τ = R_line·C_line
v(t) = Vs(1 − e^(−t/τ))

εox=3.9ε0, ε0=8.854×10⁻¹⁴ F/cm

4 · MOSFET Physics & Current

Cox = εox / tox
k'n = μn·Cox,  βn = k'n(W/L)

Triode: ID = k'n(W/L)[(VGSn−VTn)VDSn − VDSn²/2]
Saturation: ID = (βn/2)(VGSn−VTn)²
VDSn,sat = VGSn − VTn

w/ channel-length mod:
ID = (βn/2)(VGSn−VTn)²[1+λ(VDSn−VDSn,sat)]

VTn = VT0n + γ(√(2|φF|+VSBn) − √(2|φF|))
γ = √(2q·εSi·Na)/Cox
|φF| = (kT/q)ln(Na/ni)

pFET (mirror):
Triode: ID = (βp/2)[2(VSGp−|VTp|)VSDp − VSDp²]
Sat: ID = (βp/2)(VSGp−|VTp|)²
VSDp,sat = VSGp−|VTp|

5 · Scaling Theory (factor S)

6 · FET RC Model & Elmore Delay

Rn = η/[βn(VDD−VTn)]  → η=1: Rn = 1/[βn(VDD−VTn)]
Rp = 1/[βp(VDD−|VTp|)]

CG = Cox·W·L′
CGS ≈ CGD ≈ CG/2

C = C0/(1+VR/φ0)^mj , C0=Cj·Apn
φ0 = (kT/q)ln(NaNd/ni²) , mj=½ (abrupt) or ⅓ (graded)

Cbottom = Cj·X·W
Csidewall = Cjsw·Psw , Psw = 2(W+X)
Cn = Cbottom + Csidewall

CS = CGS+CSB , CD = CGD+CDB

Elmore (ladder): TD = R1C1+(R1+R2)C2+(R1+R2+R3)C3+...

Each Ci weighted by ALL upstream R.

Constants

ε0 = 8.854×10⁻¹⁴ F/cm = 8.854×10⁻¹² F/m
εSi ≈ 11.8ε0 , εox = 3.9ε0
ni = 1.45×10¹⁰ cm⁻³ , kT/q ≈ 0.026 V (300K)
mobility ratio r = μn/μp ≈ 2–3

VLSI Mid-Term — Complete Formula Sheet